一种新型高速低功耗BiC MOS分频器

本文设计了一种基于BiCMOS技术的分频器，结合了双极（Bipolar）和CMOS技术的优点。作为分频器的基本单元，锁存器的工作速度直接影响了分频器的性能。通过分离跟踪差分对与交叉耦合对，并减小后者的偏置电流可以提高锁存器的工作速度。同时，合并两个锁存器的跟踪差分对可以减小分频器的功耗。采用0．8μm BiCMOS模型在Cadence SPECTRE中仿真，可以得到这种新型高速低功耗分频器的工作频率上限可以达到2．4GHz，功耗为-1．61dBm。     

一种高速高精度CMOS电流比较器

针对传统电流比较器速度慢，精度低等问题，提出了一种新型CMOS电流比较器电路。我们采用CMOS工艺HSPICE模型参数对该电流比较器的性能进行了仿真，结果表明当电源电压为3V，输入方波电流幅度为0．3uA时，电流比较器的延时为5．2ns，而其最小分辨率仅约为0．8nA。该比较器结构简单，速度快，精度高，适合应用于高速高精度电流型集成电路中。     

应用于无线通信领域4.1 GHz锁相环的设计

在分析锁相环线性模型的基础上，分析了影响锁相环系统的各种因素，采用相应的优化方法设计了一款4.1GHz LC锁相环。详细介绍了该锁相环中各模块电路（包括Lc型压控振荡器，高速分频器，数字分频器，鉴频／鉴相器，电荷泵以及无源滤波器等）的设计，并且给出了仿真结果。其中高速分频器采用TSPC逻辑电路，速度快功耗低。该锁相环采用SMIC 0.18um CMOS工艺设计，当VCO工作在4．1GHz时，在频偏为600kHz的相位噪声为-110dBc。     

Feasibility study of the application of voltage contrast to printed circuit board

Voltage contrast (VC) has been a powerful tool for the failure analysis of integrated circuits and multichip module. As the packing density of printed circuit board (PCB) is increasing, conventional failure analysis methods to detect open or short circuit in PCBs are no longer adequate, and voltage contrast method could be a method for this purpose. However, unlike the cases of integrated circuits and multichip module, there are many areas in PCB that will produce serious charging effect when examine under the scanning electron microscope. One of the areas is the presence of solder mask on PCB.This work examines the feasibility of using voltage contrast for PCB failure analysis. Specially designed PCB is used for experimentation, and it is found that positive bias on one track and zero bias on another copper track provide a better image contrast as compared to negative and zero biases on the tracks. Also, the variation of the image contrast with different spacing between inter copper tracks has studied. It is found that the variation depends on the presence of solder mask and its location. The variation can be very different for negative bias case as compared to the positive bias case.Finite element analysis is also performed to explain the experimental observations. All the observations can be well explained by the charging effect of the solder masks. The charging effect of solder mask is indeed very significant in affecting the image contrast, and it could reduce the contrast to almost zero in some cases.     

Bulk micromachining of silicon in TMAH-based etchants for aluminum passivation and smooth surface

The fabrication of silicon based micromechanical sensors often requires bulk silicon etching after aluminum metallization. All wet silicon etchants including ordinary undoped tetramethyl ammonium hydroxide (TMAH)-water solution attack the overlaying aluminum metal interconnect during the anisotropic etching of (100) silicon. This paper presents a TMAH-water based etching recipe to achieve high silicon etch rate, a smooth etched surface and almost total protection of the exposed aluminum metallization. The etch rate measurements of (100) silicon, silicon dioxide and aluminum along with the morphology studies of etched surfaces are performed on both n-type and p-type silicon wafers at different concentrations (2, 5, 10 and 15%) for undoped TMAH treated at various temperatures as well as for TMAH solution doped separately and simultaneously with silicic acid and ammonium peroxodisulphate (AP). It is established through a detailed study that 5% TMAH-water solution dual doped with 38 gm/l silicic acid and 7 gm/l AP yields a reasonably high (100) silicon etch rate of 70 μm/h at 80 °C, very small etch rates of SiO₂ and pure aluminum (around 80 Å/h and 50 Å/h, respectively), and a smooth surface (±7 nm) at a bath temperature of 80 °C. The etchant has been successfully used for fabricating several MEMS structures like piezoresistive accelerometer, vaporizing liquid micro-thruster and flow sensor. In all cases, the bulk micromachining is carried out after the formation of aluminum interconnects which is found to remain unaffected during the prolonged etching process at 80 °C. The TMAH based etchant may be attractive in industry due to its compatibility with standard CMOS process.     

Electronic properties of GST for non-volatile memory

Impacts of annealing temperature and film thickness to the resistivity of Ge₂Sb₂Te₅(GST) have been studied. The resistivity of GST drops when the annealing temperature reaches 180 °C, rises above 360 °C and the thicker film crystallized more easily. Electronic device of phase change memory also has been fabricated with metal sidewall technology using 5 μm lithographic technology. The device was successfully programmed by 100 ns of 5 V pulse for SET and 10 ns of 10 V pulse for RESET. More than 100 times on/off ratio has been reached.     

光学和电子束曝光系统之间的匹配与混合光刻技术

介绍如何实现光学和电子束曝光系统之间的匹配和混合光刻的技术，包括：(1）光学曝光系统与电子束曝光系统的匹配技术；(2）投影光刻和JBX-5000LS混合曝光技术；(3）接触式光刻机和JBX-5000LS混合曝光技术；(4）大小束流混合曝光技术或大小光阑混合曝光技术；(5）电子束与光学曝光系统混合光刻对准标记制作技术. 该技术已成功地应用于纳米器件和集成电路的研制工作，实现了20nm线条曝光，研制成功了27nm CMOS器件；进行了50nm单电子器件的演试；并广泛地用于100nm化合物器件和其他微/纳米结构的制造.     

纳米电子器件及其集成

对基于Top-Down加工技术的纳米电子器件如：单电子器件、共振器件、分子电子器件等的研究现状、面临的主要挑战等进行了讨论. 采用CMOS兼容的工艺成功地研制出单电子器件，观察到明显的库仑阻塞效应；在半绝缘GaAs衬底上制作了AlAs/GaAs/In0.1Ga0.9As/GaAs/AlAs双势垒共振隧穿二极管,采用环型集电极和薄势垒结构研制的共振隧穿器件，在室温下测得其峰谷电流比高达13.98，峰电流密度大于89kA/cm2；概述了交叉阵列的分子存储器的研究进展.     

Effect of Pulsed Plasma Treatment on Structure and Corrosion Behavior of Sm-Co and Nd-Fe-B Magnets

The combination of conventional ion-plasma deposition and pulsed plasma technologies (PPT) has been applied for rare-earth Sm-Co and Nd-Fe-B based magnets, to provide them with enhanced corrosion resistance. The influence of pulsed plasma treatment on Sm-Co magnets with deposited titanium coatings has been investigated. It was revealed that the thickness of modified layer significantly depends on the thickness of initial titanium film and plasma treatment regimes. As a result of plasma treatment with energy density of 30 J/cm^b for 5 pulses fine-grained layer with me thickness of 70 microns has been formed on the Sm-Co magnet with pure titanium film of 50 μm. According to SEM analyses considerable diffusion of titanium to the bulk of the magnet on the depth of 20 microns took place. Such reaction enhances strong bonding between the coating and the magnet. The effects of plasma processing on corrosion properties of Nd-Fe-B sintered magnets with ferroboron Fe₈₀B₂₀ (wt.%) coatings have been studied. The tests were carried out in naturally aerated sodium sulphate solutions by polarization method. It was shown that polishing of the initial surface before plasma treatment and ferroboron deposition have a strong influence on the corrosion behavior of Nd-Fe-B magnets.     

复杂可编程逻辑器件的设计技术

介绍了复杂可编程逻辑器件（CPLD）的设计技术，重点叙述了复杂可编程逻辑器件架构的设计，关键单元设计技术。采用0．35μm内嵌Flash工艺进行模拟仿真和全定制版图设计，该复杂可编程逻辑器件（CPLD）具有72个宏单元，系统频率可达85MHz，管脚延时可达7ns。